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1 pwm dc/dc controller with vid inputs for portable gpu core-voltage regulator ISL95874, isl95875, isl95876 the ISL95874, isl95875, isl95876 ics are single-phase synchronous-buck pwm regulators featuring intersil?s proprietary r 4 technology?. the wide 3.3v to 25v input voltage range is ideal for systems that run on battery or ac-adapter power sources. the isl95875 and isl95876 are low-cost solutions for applications requiring dynamically selected slew-rate controlled output voltages. the soft-start and dynamic setpoint slew-rates are capacitor programmed. voltage identification logic-inputs se lect four (isl95875, isl95876) resistor-programmed setpoint refere nce voltages that directly set the output voltage of the converter between 0.5v and 1.5v, and up to 5v with a feedback voltage divider. compared with r 3 modulator, the r 4 modulator has equivalent light-load efficiency, faster transient performance, accurately regulated frequency control and all internal compensation. these updates, together with integrated mosfet drivers and schottky bootstrap diode, allow for a high-performance regulator that is highly compact and needs few external components. the differential remote sensing for output voltage and selectable switching frequency are another two new functions. for maximum efficiency, the converter automatically enters diode-emulation mode (dem) during light-load conditions such as system standby. features ? input voltage range: 3.3v to 25v ? output voltage range: 0.5v to 5v ? precision regulation -proprietary r 4 ? frequency control loop - 0.5% system accuracy over -10c to +100c ? optimal transient response - intersil?s r 4 ? modulator technology ?output remote sense ? extremely flexible output voltage programmability - 2-bit vid selects four independent setpoint voltages for isl95875 and isl95876 - simple resistor programming of setpoint voltages ? selectable 300khz, 500khz, 600khz or 1mhz pwm frequency in continuous conduction ? automatic diode emulation mode for highest efficiency ? power-good monitor for soft-start and fault detection applications ? mobile pc graphical processing unit vcc rail ? mobile pc i/o controller hub (ich) vcc rail ? mobile pc memory controller hub (gmch) vcc rail figure 1. ISL95874 application schematic with one output voltage setpoint and dcr current sense rtn gnd sref en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb fsel vcc pvcc lgate pgnd 11 ugate boot 2 1 12 9 pgood phase 4 3 10 +5v r vcc r pgood rtn1 r fb r ofs r ofs1 r fb1 rtn1 0 october 21, 2011 fn7933.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL95874, isl95875, isl95876 2 fn7933.0 october 21, 2011 application schematics: ISL95874 figure 2. ISL95874 application schematic with on e output voltage setpoint and dcr current sense figure 3. ISL95874 application schematic with one ou tput voltage setpoint and resistor current sense rtn gnd sref en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb fsel vcc pvcc lgate pgnd 11 ugate boot 2 112 9 pgood phase 4 310 +5v r vcc r pgood rtn1 r fb r ofs r ofs1 r fb1 rtn1 0 rtn gnd sref en c boot l o c sen r ocset q hs q ls 3.3v to 25v 0.5v to 3.3v r o co cin v in v out c soft c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo ocset fb fsel vcc pvcc lgate pgnd 11 ugate boot 2 112 9 pgood phase 4 310 +5v r vcc r pgood rtn1 r fb r ofs r sen r ofs1 r fb1 rtn1 0
ISL95874, isl95875, isl95876 3 fn7933.0 october 21, 2011 application schematics: isl95875 figure 4. isl95875 application schematic with four output voltage setpoints and dcr current sense figure 5. isl95875 application schematic with four output voltage setpoints and resistor current sense vcc boot ugate phase en pgood fsel vo pgnd gnd rtn vid1 vid0 sref set0 set1 fb lgate pvcc l o c boot c sen r ocset q hs q ls rtn1 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft r set1 r set2 r set3 c vcc +5v r vcc c pvcc gpio 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 1 10 11 20 r pgood ocset r fb r ofs r ofs1 r fb1 rtn1 0 vcc boot ugate phase en pgood fsel vo pgnd gnd rtn vid1 vid0 sref set0 set1 fb lgate pvcc l o c boot c sen r ocset q hs q ls rtn1 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft r set1 r set2 r set3 c vcc +5v c pvcc gpio 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12 1 10 11 20 r pgood ocset r fb r ofs r sen r ofs1 r fb1 rtn1 r vcc 0
ISL95874, isl95875, isl95876 4 fn7933.0 october 21, 2011 application schematics: isl95876 figure 6. isl95876 application schematic with four output voltage setpoints and dcr current sense figure 7. isl95876 application schematic with four output voltage setpoints and resistor current sense vo boot ugate phase en pgood fsel rtn vid1 vid0 sref set0 set1 pvcc vcc l o c boot c sen r ocset q hs q ls 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft c vcc +5v r vcc c pvcc gpio 1 2 3 4 5 6 15 14 13 12 11 18 9 10 17 r pgood pgnd lgate 16 7 8 20 19 r set1 r set2 r set3 r set4 r fb r ofs set2 fb ocset rtn1 r ofs1 r fb1 rtn1 gnd 0 vo boot ugate phase en pgood fsel rtn vid1 vid0 sref set0 set1 pvcc vcc l o c boot c sen r ocset q hs q ls 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft c vcc +5v r vcc c pvcc gpio 1 2 3 4 5 6 15 14 13 12 11 18 9 10 17 r pgood pgnd lgate 16 7 8 20 19 r set1 r set2 r set3 r set4 r fb r ofs set2 fb ocset r sen rtn1 r ofs1 r fb1 rtn1 gnd 0
ISL95874, isl95875, isl95876 5 fn7933.0 october 21, 2011 block diagram figure 8. simplified functional block diagram of ISL95874, isl95875, isl95876 driver driver boot ugate phase pvcc lgate pgnd overcurrent overvoltage/ soft-start circuitry r 4 modulator dead-time generation pgood circuitry reference voltage circuitry por vo ocset *set 0 *set 1 **set2 *vid1 *vid0 fb pgood sref vcc rtn en internal compensation amplifier + gnd remote sense circuitry fsel fs selection circuitry *isl95875, isl95876 only **isl95876 only undervoltage
ISL95874, isl95875, isl95876 6 fn7933.0 october 21, 2011 pin configurations ISL95874 (16 ld 2.6x1.8 utqfn) top view isl95875 (20 ld 3.2x1.8 utqfn) top view isl95876 (20 ld 3x4 qfn) top view 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 gnd rtn en sref boot ugate phase pgood pgnd lgate pvcc vcc fsel fb ocset vo 19 18 17 16 15 14 13 1 20 10 11 2 3 4 5 6 7 8 pgnd gnd rtn vid1 vid0 sref set0 vcc boot ugate phase en pgood fsel lgate pvcc fb ocset 9 set1 12 vo 10 vo 9 ocset 8 fb 7 set2 4 sref 3 vid0 1 2 20 pgnd 19 lgate 18 pvcc 17 vcc rtn vid1 5 6 set0 set1 16 15 14 13 boot ugate phase en 12 11 pgood fsel gnd
ISL95874, isl95875, isl95876 7 fn7933.0 october 21, 2011 ISL95874 functional pin descriptions pin number symbol description 1 gnd ic ground for bias supply and signal reference. 2 rtn negative remote sense input of v out . if resistor divider consisting of r fb and r ofs is used at fb pin, the same resistor divider should be used at rtn pin, i.e. keep r fb1 =r fb , and r ofs1 =r ofs . 3 en enable input for the ic. pulling en above the rising threshold voltage initializes the soft-start sequence. 4 sref soft-start and voltage slew-rate programming capacitor in put. connects internally to the inverting input of the v set voltage setpoint amplifier. 5 fsel input for programming the regulator switching frequency. pull this pin to vcc for 1mhz switching. pull this pin to gnd with a 100k resistor for 600khz switching. leave this pin floating for 500khz switching. pull this pin directly to gnd for 300khz switching. 6 fb voltage feedback sense input. connects internally to the inve rting input of the control-loop error amplifier. the converter is in regulation when the voltage at the fb pin equals the voltage on the sref pin. 7 ocset input for the overcurrent detection circuit. the overcurrent setpoint programming resistor r ocset connects from this pin to the sense node. 8 vo output voltage sense input for the r 4 modulator. the vo pin also serves as the reference input for the overcurrent detection circuit. 9 pgood power-good open-drain indicator output. this pin chan ges to high impedance when the converter is able to supply regulated voltage. 10 phase return current path for the ugate high-side mosfet driver, v in sense input for the r 4 modulator, and inductor current polarity detector input. 11 ugate high-side mosfet gate driver ou tput. connect to the gate terminal of the high-side mosfet of the converter. 12 boot positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pin and the phase pin. 13 vcc input for the ic bias voltage. connect +5v to the v cc pin and decouple with at least a mlcc to the gnd pin. 14 pvcc input for the lgate and ugate mosfet driver circuits. the pvcc pin is internally connected to the anode of the schottky boot-strap diode. connect +5v to the pvcc pin and decouple with a mlcc to the pgnd pin. 15 lgate low-side mosfet gate driver output. connect to th e gate terminal of the low-side mosfet of the converter. 16 pgnd return current path for the lgate mosfet driv er. connect to the source of the low-side mosfet.
ISL95874, isl95875, isl95876 8 fn7933.0 october 21, 2011 isl95875 functional pin descriptions pin number symbol description 1 lgate low-side mosfet gate driver output. connect to the gate terminal of the low-side mosfet of the converter. 2 pgnd return current path for the lgate mosfet driver . connect to the source of the low-side mosfet. 3 gnd ic ground for bias supply and signal reference. 4 rtn negative remote sense input of v out . if resistor divider consisting of r fb and r ofs is used at fb pin, the same resistor divider should be used at rtn pin, i.e. keep r fb1 =r fb , and r ofs1 =r ofs . 5 vid1 logic input for setpoint voltage selector. use in conjunctio n with the vid0 pin to select among four setpoint reference voltages. 6 vid0 logic input for setpoint voltage selector. use in conjunctio n with the vid1 pin to select among four setpoint reference voltages. 7 sref soft-start and voltage slew-rate programming capacitor inpu t and setpoint reference voltag e programming resistor input. connects internally to the inverting input of the v set voltage setpoint amplifier. 8 set0 voltage set-point programming resistor input. 9 set1 voltage set-point programming resistor input. 10 fb voltage feedback sense input. connects internally to th e inverting input of the control-loop error transconductance amplifier. the converter is in regulation when the volt age at the fb pin equals the voltage on the sref pin. 11 ocset input for the overcurrent detection circuit. the overcurrent setpoint programming resistor r ocset connects from this pin to the sense node. 12 vo output voltage sense input for the r 4 modulator. the vo pin also serves as the reference input for the overcurrent detection circuit. 13 fsel input for programming the regulator switching frequency. pull this pin to vcc for 1mhz switching. pull this pin to gnd with a 100k resistor for 600khz switching. leave this pin floating for 500khz switchin g. pull this pin directly to gnd for 300khz switching. 14 pgood power-good open-drain indicator ou tput. this pin changes to high impedance when the converter is able to supply regulated voltage. 15 en enable input for the ic. pulling en above the rising threshold voltage initializes the soft-start sequence. 16 phase return current path for the ugate high-side mosfet driver, v in sense input for the r 4 modulator, and inductor current polarity detector input. 17 ugate high-side mosfet gate driver output. connect to th e gate terminal of the high-side mosfet of the converter. 18 boot positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pin and the phase pin. 19 vcc input for the ic bias voltage. connect +5v to the vcc pin and decouple with at least a mlcc to the gnd pin. 20 pvcc input for the lgate and ugate mosfet driver circuits. the pvcc pin is internal ly connected to the anode of the schottky boot-strap diode. connect +5v to the pvcc pin and decouple with a mlcc to the pgnd pin.
ISL95874, isl95875, isl95876 9 fn7933.0 october 21, 2011 isl95876 functional pin descriptions pin number symbol description 1 rtn negative remote sense input of v out . if resistor divider consisting of r fb and r ofs is used at fb pin, the same resistor divider should be used at rtn pin, i.e. keep r fb1 =r fb , and r ofs1 =r ofs . 2 vid1 logic input for setpoint voltage select or. use in conjunction with the vid0 pin to select among four setpoint reference voltages. 3 vid0 logic input for setpoint voltage selector. use in conjunctio n with the vid1 pin to select among four setpoint reference voltages. 4 sref soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage programming resistor input. connects internally to the inverting input of the v set voltage setpoint amplifier. 5, 6, 7 set0, set1, set2 voltage set-point programming resistor input. 8 fb voltage feedback sense input. connects internally to th e inverting input of the control-loop error transconductance amplifier. the converter is in regulation when the volt age at the fb pin equals the voltage on the sref pin. 9 ocset input for the overcurrent detection circuit. the overcurrent setpoint programming resistor r ocset connects from this pin to the sense node. 10 vo output voltage sense input for the r 4 modulator. the vo pin also serves as the reference input for the overcurrent detection circuit. 11 fsel input for programming the regulator switching frequency. pull this pin to vcc for 1mhz switching. pull this pin to gnd with a 100k resistor for 600khz switching. leav e this pin floating for 500khz switch ing. pull this pin directly to gnd for 300khz switching. 12 pgood power-good open-drain indicator ou tput. this pin changes to high impedance when the converter is able to supply regulated voltage. 13 en enable input for the ic. pulling en above the rising threshold voltage initializes the soft-start sequence. 14 phase return current path for the ugate high-side mosfet driver, v in sense input for the r 4 modulator, and inductor current polarity detector input. 15 ugate high-side mosfet gate driver output. connect to th e gate terminal of the high-side mosfet of the converter. 16 boot positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pin and the phase pin. 17 vcc input for the ic bias voltage. connect +5v to the vcc pin and decouple with at least a mlcc to the gnd pin. 18 pvcc input for the lgate and ugate mosfet driver circuits. the pvcc pin is internally connected to the anode of the schottky boot-strap diode. connect +5v to the pvcc pin and decouple with a mlcc to the pgnd pin. 19 lgate low-side mosfet gate driver output. connect to th e gate terminal of the low-side mosfet of the converter. 20 pgnd return current path for the lgate mosfet driv er. connect to the source of the low-side mosfet. bottom pad gnd ic ground for bias supply and signal reference.
ISL95874, isl95875, isl95876 10 fn7933.0 october 21, 2011 ordering information part number (note 4) part marking temp range (c) package (pb-free) pkg. dwg. # ISL95874hruz-t (notes 1, 3) 874 -10 to +100 16 ld 2.6x1.8 utqfn l16.2.6x1.8a coming soon isl95875hruz-t (notes 1, 3) 875 -10 to +100 20 ld 3.2x1.8 utqfn l20.3.2x1.8 coming soon isl95876hrz (note 2) 876 -10 to +100 20 ld 3x4 qfn l20.3x4 coming soon isl95876hrz-t (notes 1, 2) 876 -10 to +100 20 ld 3x4 qfn l20.3x4 ISL95874iruz-t (notes 1, 3) 741 -40 to +100 16 ld 2.6x1.8 utqfn l16.2.6x1.8a coming soon isl95875iruz-t (notes 1, 3) gax -40 to +100 20 ld 3.2x1.8 utqfn l20.3.2x1.8 coming soon isl95876irz (note 2) 870i -40 to +100 20 ld 3x4 qfn l20.3x4 coming soon isl95876irz-t (notes 1, 2) 870i -40 to +100 20 ld 3x4 qfn l20.3x4 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free solder ing operations. intersil pb-fre e products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for ISL95874 , isl95875 , isl95876. for more information on msl please see techbrief tb363 .
ISL95874, isl95875, isl95876 11 fn7933.0 october 21, 2011 table of contents application schematics: ISL95874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 application schematics: isl95875. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 application schematics: isl95876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ISL95874 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 isl95875 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 isl95876 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up and voltage-step operation for ISL95874. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up and voltage-step operation for is l95875, isl95876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 output voltage programming for ISL95874. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output voltage programming for isl95875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 output voltage programming for isl95876. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 high output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 external setpoint reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 r4 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 over-temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pgood monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 integrated mosfet gate-drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 adaptive shoot-through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 general application design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 selecting the lc output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 selecting the input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 selecting the bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 driver power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mosfet selection and considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 l16.2.6x1.8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 l20.3.2x1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 l20.3x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ISL95874, isl95875, isl95876 12 fn7933.0 october 21, 2011 absolute maximum rating s thermal information vcc, pvcc, pgood, fsel to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v vcc, pvcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, set0, set1, set2, vo, vid0, vid1, fb, rtn, ocset, sref . . . . . . . . . . . . -0.3v to gnd, vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 33v boot to phase voltage (v boot-phase ). . . . . . . . . . . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 28v gnd -8v (<20ns pulse width, 10j) ugate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10j) to v boot lgate voltage . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v (dc) to vcc + 0.3v . . . . . . . . . . . . . . . . . . gnd - 2.5v (<20ns pulse width, 5j) to vcc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv latch up. . . . . . . . . . . . . . . . . . . . . . . . jedec class ii level a at +125c thermal resistance (typical) ja (c/w) jc (c/w) 16 ld utqfn (notes 5, 8) . . . . . . . . . . . . . . 95 52 20 ld utqfn (note 5) . . . . . . . . . . . . . . . . . 90 n/a 20 ld qfn (notes 6, 7) . . . . . . . . . . . . . . . . 42 5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . . -55 c to +150 c operating temperature range for ?h? version parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c for ?i? version parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range for ?h? version parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c for ?i? version parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c converter input voltage to gnd . . . . . . . . . . . . . . . . . . . . . . . . . 3.3v to 25v vcc, pvcc to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. for jc , the ?case temp? location is taken at the package top center. electrical specifications all typical specifications t a = +25c, vcc = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. parameter symbol test conditions min (note 12) typ max (note 12) unit vcc and pvcc vcc input bias current i vcc en = 5v, vcc = 5v, fb = 0.55v, sref < fb - 1.2 1.9 ma vcc shutdown current i vccoff en = gnd, vcc = 5v - 0 1.0 a pvcc shutdown current i pvccoff en = gnd, pvcc = 5v - 0 1.0 a vcc por threshold rising vcc por threshold voltage v vcc_thr 4.40 4.52 4.60 v falling vcc por threshold voltage v vcc_thf 4.10 4.22 4.35 v regulation system accuracy vid0 = vid1 = vcc, pwm mode = ccm (for ?h? version parts, t a = -10c to +100c ) -0.5 - +0.5 % vid0 = vid1 = vcc, pwm mode = ccm -0.75 +0.5 % pwm switching frequency accuracy f sw pwm mode = ccm (for ?h? version parts, t a = -10c to +100c ) -20 - +20 % pwm mode = ccm -22 - +20 % vo vo input impedance r vo en = 5v - 600 - k vo reference offset current i voss v enthr < en, sref = soft-start mode - 8.5 - a
ISL95874, isl95875, isl95876 13 fn7933.0 october 21, 2011 vo input leakage current i vooff en = gnd, vo = 3.6v - 0 - a error amplifier fb input bias current i fb en = 5v, fb = 0.50v -20 - +50 na sref (note 9) soft-start current i ss sref = soft-start mode 8.5 17 25.5 a voltage step current i vs sref = setpoint-stepping mode (for ?h? version parts, t a = -10c to +100c ) 51 85 119 a sref = setpoint-stepping mode 46 85 127 a power good pgood pull-down impedance r pg pgood = 5ma sink - 50 150 pgood leakage current i pg pgood = 5v - 0.1 1.0 a gate driver ugate pull-up resistance (note 10) r ugpu 200ma source current - 1.1 1.7 ugate source current (note 10) i ugsrc ugate - phase = 2.5v - 1.8 - a ugate sink resistance (note 10) r ugpd 250ma sink current - 1.1 1.7 ugate sink current (note 10) i ugsnk ugate - phase = 2.5v - 1.8 - a lgate pull-up resistance (note 10) r lgpu 250ma source current - 1.1 1.7 lgate source current (note 10) i lgsrc lgate - gnd = 2.5v - 1.8 - a lgate sink resistance (note 10) r lgpd 250ma sink current - 0.55 1.0 lgate sink current (note 10) i lgsnk lgate - pgnd = 2.5v - 3.6 - a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load - 21 - ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load - 21 - ns phase phase input impedance r phase - 33 - k bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma - 0.58 - v reverse leakage i r v r = 25v - 0 - a control inputs en high threshold voltage v enthr 2.0 - - v en low threshold voltage v enthf - - 1.0 v en input bias current i en en = 5v 0.85 1.7 2.55 a en leakage current i enoff en = gnd - 0 1.0 a vid<0,1> high threshold voltage (note 11) v vidthr 0.65 - - v vid<0,1> low threshold voltage (note 11) v vidthf - - 0.5 v vid<0,1> input bias current (note 11) i vid en = 5v - 0.5 - a vid<0,1> leakage current (note 11) i vidoff en=0v - 0 - a protection ocp threshold voltage v ocpth v ocset - v o -1.75 - 1.75 mv electrical specifications all typical specifications t a = +25c, vcc = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. (continued) parameter symbol test conditions min (note 12) typ max (note 12) unit
ISL95874, isl95875, isl95876 14 fn7933.0 october 21, 2011 ocp reference current i ocp en = 5.0v (for ?h? version parts, t a = -10c to +100c ) 7.65 8.5 9.35 a en = 5.0v 7.05 8.5 9.35 a ocset input resistance r ocset en = 5.0v - 600 - k ocset leakage current i ocset en = gnd - 0 - a uvp threshold voltage v uvth v fb = %v sref 81 84 87 % ovp rising threshold voltage v ovrth v fb = %v sref (for ?h? version parts, t a = -10c to +100c ) 113 116 120 % v fb = %v sref 112.5 116 120 % ovp falling threshold voltage v ovfth v fb = %v sref 98 102 106 % otp rising threshold temperature (note 10) t otrth - 150 - c otp hysteresis (note 10) t othys - 25 - c notes: 9. for ISL95874,there is one internal reference 0.5v. for isl958 75, isl95876, there are four resistor-programmed reference volta ges. 10. limits established by characterization and are not production tested. 11. vid function is only for isl95875, isl95876. 12. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperatur e limits established b y characterization and are not production tested. electrical specifications all typical specifications t a = +25c, vcc = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. (continued) parameter symbol test conditions min (note 12) typ max (note 12) unit
ISL95874, isl95875, isl95876 15 fn7933.0 october 21, 2011 theory of operation the following sections will provide a detailed description of the ISL95874, isl95875, isl95876 internal operation. power-on reset the ic is disabled until the voltage at the vcc pin has increased above the rising power-on reset (por) threshold voltage v vcc_thr . the controller will disable when the voltage at the vcc pin decreases below the falling por threshold voltage v vcc_thf . the por detector has a noise filter of approximately 1s. start-up timing once vcc has ramped above v vcc_thr , the controller will be enabled by pulling the en pin voltage above the input-high threshold v enthr . in approximately 20s, the voltage at the sref pin begins slewing to the designated vid set-point. the converter output voltage at the fb feedback pin follows the voltage at the sref pin. during soft-start, the regulator always operates in ccm until the soft-start sequence is complete. start-up and voltage-step operation for ISL95874 when the voltage on the vcc pin has ramped above the rising power-on reset voltage v vcc_thr , and the voltage on the en pin has increased above the rising enable threshold voltage v enthr , the sref pin releases its disc harge clamp, and enables the reference amplifier v set . the soft-start current i ss is limited to 17a and is sourced out of the sref pin and charges capacitor c soft until v sref equals v ref . the regulator controls the pwm such that the voltage on the fb pin tracks the rising voltage on the sref pin. the elapsed time from when the en pin is asserted to when v sref has charged c soft to v ref is called the soft-start delay t ss , which is given by equation 1: where: -i ss is the soft-start current source at the 17a limit -v sref is the buffered v ref reference voltage the end of soft-start is detected by i ss tapering off when capacitor c soft charges to v ref . the internal ssok flag is set, the pgood pin goes high, and diode emulation mode (dem) is enabled. choosing the c soft capacitor to meet the requirements of a particular soft-start delay t ss is calculated using equation 2: where: -t ss is the soft-start delay -i ss is the soft-start current source at the 17a limit -v sref is the buffered v ref reference voltage start-up and voltage-step operation for isl95875, isl95876 when the voltage on the vcc pin has ramped above the rising power-on reset voltage v vcc_thr , and the voltage on the en pin has increased above the rising enable threshold voltage v enthr , the sref pin releases its discharge clamp and enables the reference amplifier v set . the soft-start current i ss is limited to 17a and is sourced out of the sref pin into the parallel rc network of capacitor c soft and resistance r t . the resistance r t is the sum of all the series connected r set programming resistors and is written as equation 3: the voltage on the sref pin rises as i ss charges c soft to the voltage reference setpoint selected by the state of the vid inputs at the time the en pin is asserted. the regulator controls the pwm, such that the voltage on the fb pin tracks the rising voltage on the sref pin. once c soft charges to the selected setpoint voltage, the i ss current source comes out of th e 17a current limit and decays to the static value set by v sref /r t . the elapsed time from when the en pin is asserted to when v sref has reached the voltage reference setpoint is the soft-start delay t ss , which is given by equation 4: where: -i ss is the soft-start current source at the 17a limit -v start-up is the setpoint reference voltage selected by the state of the vid inputs at the time en is asserted -r t is the sum of the r set programming resistors the end of soft-start is detected by i ss tapering off when capacitor c soft charges to the designated v set voltage reference setpoint. the ssok flag is set, and the pgood pin goes high. the i ss current source changes over to the voltage-step current source i vs , which has a current limit of 85a. whenever the vid inputs or the external setpoint reference programs a different setpoint reference voltage, the i vs current source charges or discharges capacitor c soft to that new level at 85a. once c soft charges to the selected setpoint voltage, the i vs current source comes out of the 85a cu rrent limit and decays to the static value set by v sref /r t . the elapsed time to charge c soft to the new voltage is called the voltage-step delay t vs and is given by equation 5: t ss v sref c soft ? i ss ------------------------------------- = (eq. 1) s oft t ss i ss ? v sref -------------------- - = (eq. 2 r t r set1 r set2 r set n () ++ = (eq. 3) t ss r t c soft ? () ? ln 1 v start-up i ss r t ? ------------------------- ? () ? = (eq. 4) t vs r t c soft ? () ? ln 1 v new v old ? () i vs r t ? --------------------------------------- ? () ? = (eq. 5)
ISL95874, isl95875, isl95876 16 fn7933.0 october 21, 2011 where: -i vs is the 85a setpoint voltage-step current; positive when v new > v old , negative when v new < v old -v new is the new setpoint voltage selected by the vid inputs -v old is the setpoint voltage that v new is changing from -r t is the sum of the r set programming resistors choosing the c soft capacitor to meet the requirements of a particular soft-start delay t ss is calculated with equation 6, where: -t ss is the soft-start delay -i ss is the soft-start current source at the 17a limit -v start-up is the setpoint reference voltage selected by the state of the vid inputs at the time en is asserted -r t is the sum of the r set programming resistors choosing the c soft capacitor to meet the requirements of a particular voltage-step delay t vs is calculated with equation 7, where: -t vs is the voltage-step delay -v new is the new setpoint voltage -v old is the setpoint voltage that v new is changing from -i vs is the 85a setpoint voltage-step current; positive when v new > v old , negative when v new < v old -r t is the sum of the r set programming resistors output voltage programming for ISL95874 the ISL95874 has a fixed 0.5v reference voltage (v sref ). as shown in figure 9, the output voltage is the reference voltage if r fb is shorted and r ofs is open. a resistor divider consisting of r ofs and r fb allows the user to scale the output voltage between 0.5v and 5v. the relation between the output voltage and the reference voltage is given in equation 8: output voltage prog ramming for isl95875 the isl95875 allows the user to select four different reference voltages, thus four different output voltages, by voltage identification pins vid1 and vi d0. the maximum reference voltage cannot be designed higher than 1.5v. the implementation scheme is shown in figure 10. the setpoint reference voltages are programmed with resistors that use the naming convention r set(x) where (x) is the first, second, or third programming resistor connected in series starting at the sref pin and ending at the gnd pin. as shown in table 1, differen t combinations of vid1 and vid0 closes different switches and le aves other switches open. for example, for the case of vid1 = 1 and vid0 = 0, switch sw1 closes and all the other three switches sw0, sw2 and sw3 are open. for one combination of vid1 and vid0, the internal switch connects the inverting input of the v set amplifier to a specific node among the string of r set programming resistors. all the resistors between that node and the sref pin serv e as the feedback impedance r f of the v set amplifier. likewise, all the resistors between that node and the gnd pin serve as the input impedance r in of the v set amplifier. equation 9 gives the gene ral form of the gain equation for the v set amplifier: where: -v ref is the 0.5v internal reference of the ic -v setx is the resulting setpoint reference voltage that appears at the sref pin c soft t ss ? r t ln 1 v start-up i ss r t ? ------------------------- ? () ? ?? ?? ?? -------------------------------------------------------------- - = (eq. 6) c soft t vs ? r t ln 1 v new v old ? i vs r t ? ---------------------------------- ? () ? ?? ?? ?? ------------------------------------------------------------------------ = (eq. 7) v out v sref r fb r ofs + r ofs ------------------------------ ? = (eq. 8) table 1. isl95875 vid truth table vid state result vid1 vid0 close v sref v out 11sw0v set1 v out1 figure 9. ISL95874 voltage programming circuit sref v set + ? v ref c soft ea + ? fb r ofs r fb v out v comp setx v ref 1 r f r in -------- - + ?? ?? ?? ? = (eq. 9
ISL95874, isl95875, isl95876 17 fn7933.0 october 21, 2011 equations 10, 11, 12 and 13 give the specific v set equations for the isl95875 setpoint reference voltages. the isl95875 v set1 setpoint is written as equation 10: the isl95875 v set2 setpoint is written as equation 11: the isl95875 v set3 setpoint is written as equation 12: the isl95875 v set4 setpoint is written as equation 13: the v set1 is fixed at 0.5v because it corresponds to the closure of internal switch sw0 that configures the v set amplifier as a unity-gain voltage follower for the 0.5v voltage reference v ref . theoretically, v set3 can be higher or lower or equal to v set4 depending on the selection of r set1 , r set2 and r set3 . however, it is recommended to design the four reference voltages in the following order: -v set1 < v set2 < v set3 < v set4 thus, -v out1 < v out2 < v out3 < v out4 for the four given user selected reference voltages v setx , equation 14 needs to be satisfied in order to have non-zero solution for r setx . the programmed resistors r set1 , r set2 and r set3 are designed in the following way. first, assign an initial value to r set3 of approximately 100k then calculate r set1 and r set2 using equations 15 and 16 respectively. if additional flexibility is required in selecting v set4 , then a fourth resistor, r set4 , can be added between the set1 pin and the r set2 and r set3 resistors, see figure 11 on page 18. the addition of this resistor allows adjustment of reference only when sw3 is closed. the isl95875 vset4 reference setpoint is defined in equation 17: the sum of all the programming resistors must be 300k or greater , as shown in equation 18, otherwise adjust the value of r set3 and repeat the calculations. if the output voltage is in the range of 0.5v to 1.5v, the external resistor-divider is not necessary. the output voltage is equal to one of the reference voltages depending on the status of vid1 and vid0. the external resist or divider consisting of r fb and r ofs allows the user to program th e output voltage in the range of 1.5v to 5v. the relation between the output voltage and the reference voltage is given in equation 19: in this case, the four output voltages are equal to each of the corresponding reference voltages multiplying the factor k. 10sw1v set2 v out2 01sw2v set3 v out3 00sw1, sw3v set4 v out4 table 1. isl95875 vid truth table (continued) vid state result vid1 vid0 close v sref v out figure 10. isl95875 voltage programming circuit set0 sref v set + ? sw0 v ref set1 sw1 sw2 sw3 c soft r set1 r set2 r set3 ea + ? fb r ofs r fb v out v comp 0.5v v set1 v ref = (eq. 10) v set2 v ref 1 r set1 r set2 r set3 + --------------------------------------- + ?? ?? ?? ? = (eq. 11) v set3 v ref 1 r set1 r set2 + r set3 --------------------------------------- + ?? ?? ?? ? = (eq. 12) v set4 v ref 1 r set1 r set2 ---------------- + ?? ?? ?? ? = (eq. 13) v set1 v set2 ? v + set3 v set4 ? v ? set2 v set3 ? v ? set2 v set4 ? 0 = (eq. 14) r set1 r set3 v set4 v ref ? () v set2 v ref ? () ?? v ref v set4 v set2 ? () ? --------------------------------------------------------------------------------------------------------- = (eq. 15) r set2 r set3 v set2 v ref ? () ? v set4 v set2 ? ------------------------------------------------------------ - = (eq. 16) v set4 v ref 1 r set1 r set2 r set3 r set4 ? r set3 r set4 + --------------------------------------- ?? ?? ?? + -------------------------------------------------------------------- + ?? ?? ?? ?? ?? ?? ?? ? = (eq. 17) r set1 r set2 r set3 ++ 300k (eq. 18) v out v sref r fb r ofs + r ofs ------------------------------ ? v sref k ? == (eq. 19) v outx v setx k ? = (eq. 20)
ISL95874, isl95875, isl95876 18 fn7933.0 october 21, 2011 output voltage programming for isl95876 the isl95876 allows the user to select four different reference voltages, thus four different output voltages, by voltage identification pins vid1 an d vid0. the maximum reference voltage cannot be designed higher than 1.5v. the implementation scheme is shown in figure 12. the setpoint reference voltages are programmed with resistors that use the naming convention r set(x) where (x) is the first, second, third, or fourth programming resistor connect ed in series starting at the sref pin and ending at the gnd pin. as shown in table 2, different combinations of vid1 an d vid0 close different switches and leave other switches open. for example, for the case of vid1 = 1 and vid0 = 0, switch sw1 closes and all the other three switches sw0, sw2 and sw3 are open. for one combination of vid1 and vid0, the internal switch connects the inverting input of the v set amplifier to a specific no de among the string of r set programming resistors. all the resistors between that node and the sref pin serve as the feedback impedance r f of the v set amplifier. likewise, all the resi stors between that node and the gnd pin serve as the input impedance r in of the v set amplifier. equation 21 gives the general form of the gain equation for the v set amplifier: where: -v ref is the 0.5v internal reference of the ic -v setx is the resulting setpoint reference voltage that appears at the sref pin equations 22, 23, 24 and 25 give the specific v set equations for the isl95876 setpoint reference voltages. the isl95876 v set1 setpoint is written as equation 22: the isl95876 v set2 setpoint is written as equation 23: the isl95876 v set3 setpoint is written as equation 24: the isl95876 v set4 setpoint is written as equation 25: the v set1 is fixed at 0.5v because it corresponds to the closure of internal switch sw0 that configures the v set amplifier as a unity-gain voltage follower for the 0.5v voltage reference v ref . the setpoint reference voltages use the naming convention v set(x) where (x) is the first, second, third, or fourth setpoint reference voltage where: -v set1 < v set2 < v set3 < v set4 thus, -v out1 < v out2 < v out3 < v out4 for the given four user selected reference voltages v setx , the programmed resistors r set1 , r set2 , r set3 and r set4 are designed in the following way. firs t, assign an initial value to r set4 of approximately 100k then calculate r set1, r set2 and r set3 using equations 26, 27, and 28 respectively. figure 11. isl95875 optional r set4 resistor set0 sref v set + ? sw0 v ref set1 sw1 sw2 sw3 c soft r set1 r set2 r set3 ea + ? fb r ofs r fb v out v comp 0.5v r set4 v setx v ref 1 r f r in -------- - + ?? ?? ?? ? = (eq. 21) table 2. isl95876 vid truth table vid state result vid1 vid0 close v sref v out 11sw0v set1 v out1 10sw1v set2 v out2 01sw2v set3 v out3 00sw3v set4 v out4 v set1 v ref = (eq. 22) v set2 v ref 1 r set1 r set2 r set3 r set4 ++ -------------------------------------------------------------- + ?? ?? ?? ? = (eq. 23) v set3 v ref 1 r set1 r set2 + r set3 r set4 + --------------------------------------- + ?? ?? ?? ? = (eq. 24) v set4 v ref 1 r set1 r set2 r + set3 + r set4 -------------------------------------------------------------- + ?? ?? ?? ? = (eq. 25) r set1 r set4 v set4 v set2 v ref ? () ?? v ref v set2 ? --------------------------------------------------------------------------------- = (eq. 26) r set2 r set4 v set4 v set3 v set2 ? () ?? v set2 v set3 ? ------------------------------------------------------------------------------------ = (eq. 27) r set3 r set4 v set4 v set3 ? () ? v set3 --------------------------------------------------------------- - = (eq. 28)
ISL95874, isl95875, isl95876 19 fn7933.0 october 21, 2011 the sum of all the programming resistors must be 300k or greater , as shown in equation 29, otherwise adjust the value of r set4 and repeat the calculations. if the output voltage is in the range of 0.5v to 1.5v, the external resistor-divider is not necessary. the output voltage is equal to one of the reference voltages de pending on the status of vid1 and vid0. the external resistor divider consisting of r fb and r ofs allows the user to program the output voltage in the range of 1.5v to 5v. the relation be tween the output voltage and the reference is given in equation 30: in this case, the four output voltages are equal to each of the corresponding reference voltages multiplying the factor k. high output voltage programming the ISL95874 has a fixed 0.5v reference voltage (v sref ). for high output voltage application, the re sistor divider consisting of r fb and r ofs requires a large ratio (r fb :r ofs = 9:1 for 5v output). the fb pin with large ratio resistor divider is noise sensitive and the pcb layout should be carefully routed. it is recommended to use small value resistor divider such as r fb =1k . in general, the isl95875 and isl95876 have much better jitter performance than the ISL95874 when the output voltage is in the range of 3.3v to 5v, particularly in dcm. this is because v sref voltage can be set to 1.5v and a smaller ratio resistor divider can be used. this makes the signal-to-noise ratio at fb pin much better. so for 3.3v to 5v output, the isl95875 and isl95876 are recommended with v sref set to 1.5v. external setpoint reference the isl95875 and isl95876 can use an external setpoint reference voltage as an al ternative to vid-selected, resistor-programmed setpoints. this is accomplished by removing all setpoint programm ing resistors, connecting the set0 pin to the vcc pin, and feeding the external setpoint reference voltage to the vid0 pin. when set0 and vcc are tied together, the following internal reconfigurations take place: - vid0 pin opens its 500na pull-down current sink - an internal switch changes position from the internal reference source of 500mv to the vid0 pin and accepts an external reference. - vid1 pin is disabled the converters will now be in regulation when the voltage on the fb pin equals the voltage on the vid0 pin. as with resistor-programmed setpoints, the reference voltage range on the vid0 pin is 500mv to 1.5v. use equation 8 should it become necessary to implement an output voltage-divider network to make the external setpoint refe rence voltage compatible with the 500mv to 1.5v constraint. r4 modulator the r 4 modulator is an evolutionary step in r 3 technology. like r 3 , the r 4 modulator allows variable frequency in response to load transients and maintains the benefits of current-mode hysteretic controllers. however, in addition, the r 4 modulator reduces regulator output impedance and uses accurate referencing to eliminate the need for a high-gain voltage amplifier in the compensation loop. the result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control model and removes the need for any compensation. this greatly simpli fies the regulator design for customers and reduces external component cost. stability the removal of compensation derives from the r 4 modulator?s lack of need for high dc gain. in traditional architectures, high dc gain is achieved with an integrator in the voltage loop. the integrator introduces a pole in th e open-loop transfer function at low frequencies. thus, when comb ined with the double-pole from the output l/c filter, creates a three pole system that must be compensated to maintain stability. classic control theory requires a single-pole tran sition through unity gain to ensure a stable sy stem. current-mode architectures (includes peak, peak-valley, current-mode hysteretic, r 3 and r 4 ) generate a zero at or near the l/c resonant point, effectively canceling one of the system?s po les. the system still contains two poles, one of which must be canceled with a zero before unity gain crossover to achieve stability. compensation components are added to introduce the necessary zero. r set1 r set2 r set3 r set4 +++ 300k (eq. 29) figure 12. isl95876 voltage programming circuit set2 set0 sref v set + ? sw0 v ref set1 sw1 sw2 sw3 c soft r set1 r set2 r set3 r set4 ea + ? fb r ofs r fb v out v comp 0.5v v out v sref r fb r ofs + r ofs ------------------------------ ? v sref k ? == (eq. 30) v outx v setx k ? = (eq. 31)
ISL95874, isl95875, isl95876 20 fn7933.0 october 21, 2011 figure 13 illustrates the classic integrator configuration for a voltage loop error-amplifier. while the integrator provides the high dc gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. figure 14 shows the open-loop response that results from the addition of an integrat ing capacitor in the voltage loop. the compensation components foun d in figure 13 are necessary to achieve stability. because r 4 does not require a high-gain voltage loop, the integrator can be removed, reducing the number of inherent poles in the loop to two. the current-mode zero continues to cancel one of the poles, ensuri ng a single-pole crossover for a wide range of output filter choice s. the result is a stable system with no need for compensation components or complex equations to properly tune the stability. figure 15 shows the r 4 error-amplifier that does not require an integrator for high dc gain to achieve accurate regulation. the result to the open loop respon se can be seen in figure 16. transient response in addition to requiring a compen sation zero, the integrator in traditional architecture s also slows system re sponse to transient conditions. the change in comp voltage is slow in response to a rapid change in output voltage. if the integrating capacitor is removed, comp moves as quickly as v out , and the modulator immediately increases or decr eases switching frequency to recover the output voltage. the dotted red and blue lines in figure 17 represent the time delayed behavior of v out and v comp in response to a load transient when an integrator is used. the solid red and blue lines illustrate the increased response of r 4 in the absence of the integrator capacitor. diode emulation the polarity of the output inductor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. the dc component of the inductor current is positive, but the ac component known as the ripple curren t, can be either positive or negative. should the sum of the ac and dc components of the inductor current remain positive for the entire switching period, figure 13. integrator error-amplifier configuration v v comp integrator for high dc gain compensation to counter integrator pole v out v dac v comp figure 14. uncompensated integrator open-loop response f (hz) p1 p2 p3 l/c double-pole integrator pole z1 zero - 6 0 d b / d e c - 20 d b /dec -20db crossover required for stability compensator to add z2 is needed - 4 0 d b / d e c r3 loop gain (db) current-mode figure 15. non-integrated r4 error-amplifier configuration v out v dac r1 r2 v comp figure 16. uncompensated r4 open-loop response f (hz) p1 p2 l/c double-pole z1 current-mode zero -20db/dec system has 2 poles and 1 zero no compensator is needed r4 loop gain (db) -20db / de c - 4 0 d b / d e c figure 17. r3 vs r4 idea lized transient response r3 i t v comp r4 t t i out t t t v out
ISL95874, isl95875, isl95876 21 fn7933.0 october 21, 2011 the converter is in continuous-conduction-mode (ccm). however, if the inductor current becomes ne gative or zero, the converter is in discontinuous-conduction-mode (dcm). unlike the standard dc/dc buck regulator, the synchronous rectifier can sink current from the output filter inductor during dcm, reducing the light-load efficiency with unnecessary conduction loss as the low-side mosfet sinks the inductor current. the ISL95874, isl95875, isl95876 controllers avoid the dcm conduction loss by making the low-side mosfet emulate the current-blocking beha vior of a diode. this smart- diode operation called diode-emulation-mode (dem) is triggered when the negative inductor current produces a positive voltage drop across the r ds(on) of the low-side mosfet for eight consecutive pwm cycles while the lgate pin is high. the converter will exit dem on the next pwm pulse after detecting a negative voltage across the r ds(on) of the low-side mosfet. it is characteristic of the r 4 architecture for the pwm switching frequency to decrease while in dcm, increasing efficiency by reducing unnecessary gate-driver switching losses. the extent of the frequency reduction is proporti onal to the reduction of load current. upon entering dem, the pwm frequency is forced to fall approximately 30% by forcing a si milar increase of the window voltage v w . this measure is taken to prevent oscillating between modes at the boundary between ccm and dcm. the 30% increase of v w is removed upon exit of dem, forcing the pwm switching frequency to jump back to the nominal ccm value. overcurrent the overcurrent protection (ocp) setpoint is programmed with resistor r ocset , which is connected across the ocset and phase pins. resistor r o is connected between the vo pin and the actual output voltage of the converter. during normal operation, the vo pin is a high impedance path, therefore there is no voltage drop across r o . the value of resistor r o should always match the value of resistor r ocset . figure 18 shows the overcurrent se t circuit. the inductor consists of inductance l and the dc resistance dcr. the inductor dc current i l creates a voltage drop across dcr, which is given by equation 32: the i ocset current source sinks 8.5a into the ocset pin, creating a dc voltage dr op across the resistor r ocset , which is given by equation 33: the dc voltage difference between the ocset pin and the vo pin, which is given by equation 34: the ic monitors the voltage of the ocset pin and the vo pin. when the voltage of the ocset pin is higher than the voltage of the vo pin for more than 10s, an ocp fault latches the converter off. the value of r ocset is calculated with equation 35, written as: where: -r ocset ( ) is the resistor used to program the overcurrent setpoint -i oc is the output dc load curren t that will activate the ocp fault detection circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m , the choice of r ocset is equal to 20a x 4.5m /8.5a = 10.5k . resistor r ocset and capacitor c sen form an r-c network to sense the inductor current. to sense the inductor current correctly not only in dc operat ion, but also during dynamic operation, the r-c network time constant r ocset c sen needs to match the inductor time constant l/dcr. the value of c sen is then written as equation 36: for example, if l is 1.5h, dcr is 4.5m , and r ocset is 9k , the choice of c sen = 1.5h/(9k x 4.5m ) = 0.037f . when an ocp fault is declared, the converter will be latched off and the pgood pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . overvoltage the ovp fault detection circuit triggers after the fb pin voltage is above the rising overvoltage threshold v ovrth for more than 2s. for example, if the converter is programmed to regulate 1.0v at the fb pin, that voltage would have to rise above the typical v ovrth threshold of 116% for more than 2s in order to trip the ovp fault latch. in numeri cal terms, that would be 116% x 1.0v = 1.16v. when an ovp fault is declared, the converter will be latched off and the pgood pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the fallin g por threshold voltage v vcc_thf . although the converter has latched-off in response to an ovp fault, the lgate gate-driver output will retain the ability to toggle figure 18. overcurrent programming circuit phase c o l v o r ocset c sen ocset vo r o dcr i l 8.5a + _ v dcr + _ v rocset v dcr i l dcr ? = (eq. 32) v rocset 8.5 ar ocset ? = (eq. 33) v ocset v ? vo v dcr v ? rocset i l dcr ? i ocset r ocset ? ? == (eq. 34) (eq. 35) r ocset i oc dcr ? i ocset ------------------------ - = (eq. 36) c sen l r ocset dcr ? ------------------------------------ - =
ISL95874, isl95875, isl95876 22 fn7933.0 october 21, 2011 the low-side mosfet on and off, in response to the output voltage transversing the v ovrth and v ovfth thresholds. the lgate gate-driver will turn-on the low-side mosfet to discharge the output voltage, protecting th e load. the lgate gate-driver will turn-off the low-side mosfet once the fb pin voltage is lower than the falling overvoltage threshold v ovrth for more than 2s. the falling overvoltage threshold v ovfth is typically 102%. that means if the fb pin voltage fa lls below 102% x 1.0v = 1.02v for more than 2s, the lgate gate-d river will turn off the low-side mosfet. if the output voltage rises again, the lgate driver will again turn on the low-side mosf et when the fb pin voltage is above the rising overvoltage threshold v ovrth for more than 2s. by doing so, the ic protects the load when there is a consistent overvoltage condition. undervoltage the uvp fault detection circuit triggers after the fb pin voltage is below the undervoltage threshold v uvth for more than 2s. for example if the converter is programmed to regulate 1.0v at the fb pin, that voltage would have to fall below the typical v uvth threshold of 84% for more than 2s in order to trip the uvp fault latch. in numerical terms, that would be 84% x 1.0v = 0.84v. when a uvp fault is declared, the converter will be latched off and the pgood pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . over-temperature when the temperature of the ic increases above the rising threshold temperature t otrth , it will enter the otp state that suspends the pwm, forcing the lgate and ugate gate-driver outputs low. the status of the pgood pin does not change nor does the converter latch-off. the pwm remains suspended until the ic temperature falls below the hysteresis temperature t othys at which time normal pwm operation resumes. the otp stat e can be reset if the en pin is pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . all other protection circuits remain functional while the ic is in the otp state. it is likely that the ic will detect an uvp fault because in the absence of pwm, the output voltage decays below the undervoltage threshold v uvth . pgood monitor the pgood pin indicates when the converter is capable of supplying regulated voltage. the pgood pin is an undefined impedance if the vcc pin has not reached the rising por threshold v vcc_thr , or if the vcc pin is below the falling por threshold v vcc_thf . if there is a fault condition of output overcurrent, overvoltage or undervoltage, pgood is asserted low. the pgood pull-down impedance is 50 . integrated mosfet gate-drivers the lgate pin and ugate pins are mosfet driver outputs. the lgate pin drives the low-side mosfet of the converter while the ugate pin drives the high-side mosfet of the converter. the lgate driver is optimized for low duty-cycle applications where the low-side mosfet experi ences long conduction times. in this environment, the low-side mosfets require exceptionally low r ds(on) and tend to have large parasitic charges that conduct transient currents within the devi ces in response to high dv/dt switching present at the phase node. the drain-gate charge in particular can conduct sufficie nt current through the driver pull-down resistance that the v gs(th) of the device can be exceeded and turned on. for this reason, the lgate driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the mosfets gate voltage below v gs(th) . adaptive shoot-through protection adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 19 is extended by the additional period that the falling gate voltage remains above the 1v threshold. the high-side gate-driver output voltage is measured across the ugate and phase pins while the low-side gate-driver output voltage is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the pvcc pin. the-power for the ugate gate-driver is supplied by a boot-strap capacitor connected across the boot and phase pins. the capacitor is charged each time the phase node voltage falls a diode drop below pvcc such as when the low-side mosfet is turned on. figure 19. gate drive adaptive shoot-through protection 1v 1v ugate lgate 1v 1v
ISL95874, isl95875, isl95876 23 fn7933.0 october 21, 2011 general application design guide this design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase buck converter. it is assumed that the reader is familia r with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck converter is a function of the input and the output voltage. this relationship is expressed in equation 37: the output inductor peak-to-peak ripple current is expressed in equation 38: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several criteria such as mosfet switching loss, inductor core loss, and th e resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated using equation 39: where, i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr of the inductor. another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. a saturated inductor could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into, which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are expressed in equations 40 and 41: if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can significantly impact the output voltage ripple and cause a brief volt age spike if the load transient has an extremely high slew rate. low inductance capacitors should be considered. a capacitor dissipa tes heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fa de as much as 50% as the dc voltage across it increases. selecting the input capacitor the important parameters for the bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capabl e of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 20 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. the ripple current calculation is written as equation 42: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter duty cycle is written as equation 43: in addition to the bulk capacitors, some low esl ceramic capacitors are recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. selecting the bootstrap capacitor the integrated driver features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor voltage rating is selected to be at least 10v. although the theoretical maximum voltage of the capacitor is pvcc-v diode (voltage drop across the boot diode), large excursions below ground by the phase node requires at least a 10v rating for the bootstrap capacitor. th e bootstrap capacitor can be chosen from equation 44: d v o v in -------- = (eq. 37) (eq. 38) i p-p v o 1d ? () ? f sw l ? ----------------------------- = (eq. 39) p copper i load 2 dcr ? = v esr i p-p e ? sr = (eq. 40) v c i p-p 8c o f ? sw ? ------------------------------ = (eq. 41) (eq. 42) i in_rms i max 2 dd 2 ? () ? () x 2 i max 2 d 12 ------ - ?? ?? ?? + i max ----------------------------------------------------------------------------------------------------- - = (eq. 43) d v o v in eff ? ---------------------- - = figure 20. normalized input rms current for eff = 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 duty cycle normalized input rms ripple current x = 0.5 x = 0 x = 1
ISL95874, isl95875, isl95876 24 fn7933.0 october 21, 2011 where: -q gate is the amount of gate charge required to fully charge the gate of the upper mosfet - v boot is the maximum decay across the boot capacitor as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffice. use a low temperature-coefficient ceramic capacitor. driver power dissipation switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of +125c. when designing the application, it is recommended th at the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the drivers is approximated as equation 45: where: -f sw is the switching frequency of the pwm signal -v u is the upper gate driver bias supply voltage -v l is the lower gate driver bias supply voltage -q u is the charge to be delivered by the upper driver into the gate of the mosfet and discrete capacitors -q l is the charge to be delivered by the lower driver into the gate of the mosfet and discrete capacitors -p l is the quiescent power consumption of the lower driver -p u is the quiescent power cons umption of the upper driver mosfet selection and considerations the choice of mosfets depends on the current each mosfet will be required to conduct, the switch ing frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain to source vo ltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltag e spike that occurs when the mosfets switch. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. for the low-side mosfet, (ls), the power loss can be assumed to be conductive only and is written as equation 46: for the high-side mosfet, (hs), it s conduction loss is written as equation 47: for the high-side mosfet, its switching loss is written as equation 48: where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off layout considerations as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. the ground-plane layer should be adjacent to the signal layer to provide shielding. the ground plane layer should have an island located under the ic, the components connected to analog or logic signals. the island should be connected to th e rest of the ground plane layer at one quiet point. there are two sets of components in a dc/dc converter, the power components and the small signal components. the power components are the most critical because they switch large amount of energy. the small si gnal components connect to c boot q gate v boot -------------------- - (eq. 44) pf sw 1.5v u q u v l q l + () p l p u ++ = (eq. 45) figure 21. power dissipation vs frequency frequency (hz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k power (mw) q u =50nc q l =50nc q u =20nc q l =50nc q u =50nc q l =100nc q u =100nc q l =200nc (eq. 46) p con_ls i load 2 r ? ds on () _ls 1d ? () ? (eq. 47) p con_hs i load 2 r ? ds on () _hs d ? = (eq. 48) p sw_hs v in i valley t on f ? sw ?? 2 --------------------------------------------------------------- v in i peak t off f ? sw ?? 2 ------------------------------------------------------------ + =
ISL95874, isl95875, isl95876 25 fn7933.0 october 21, 2011 sensitive nodes or supply critic al bypassing current and signal coupling. the power components should be placed first and these include mosfets, input and output capacitors, and the inductor. keeping the distance between the power train and the control ic short helps keep the gate drive traces short. these drive signals include the lgate, ugate, pgnd, phase and boot. when placing mosfets, try to keep the source of the upper mosfets and the drain of the lower mosfets as close as thermally possible. see figure 22. input high frequency capacitors should be placed cl ose to the drain of the upper mosfets and the source of the lower mosfets. place the output inductor and output capacitors between the mosfets and the load. high frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target, making use of the shortest co nnection paths to any internal planes. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. vcc and pvcc pins place the decoupling capacitors as close as practical to the ic. in particular, the pvcc decoupling capacitor should have a very short and wide connection to th e pgnd pin. the vcc decoupling capacitor should be referenced to gnd pin. en, pgood, vid0, vid1, and fsel pins these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. ocset and vo pins the current-sensing network consisting of r ocset , r o , and c sen needs to be connected to the inductor pads for accurate measurement of the dcr voltage drop. these components however, should be located physically close to the ocset and vo pins with traces leading back to th e inductor. it is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. the procedure is the same for resistive current sense. fb, sref, set0, set1, set2, and rtn pins the input impedance of these pins is high, making it critical to place the components connected to these pins as close as possible to the ic. lgate, pgnd, ugate, boot, and phase pins the signals going through these tr aces are high dv/dt and high di/dt, with high peak charging and discharging current. the pgnd pin can only flow current from the gate-source charge of the low-side mosfets when lgate goes low. ideally, route the trace from the lgate pin in parall el with the trace from the pgnd pin, route the trace from the ugate pin in parallel with the trace from the phase pin. in order to have more accurate zero-crossing detection of inductor current, it is recommended to connect phase pin to the drain of the low-side mosfets with kelvin connection. these pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximit y with these traces on any layer. inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets figure 22. typical power component placement
ISL95874, isl95875, isl95876 26 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7933.0 october 21, 2011 for additional products, see www.intersil.com/product_tree revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL95874 , isl95875 , isl95876 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php date revision change october 21, 2011 fn7933.0 initial release.
ISL95874, isl95875, isl95876 27 fn7933.0 october 21, 2011 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 k l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - k0.15 - - - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0-12 4 rev. 5 2/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.
ISL95874, isl95875, isl95876 28 fn7933.0 october 21, 2011 package outline drawing l20.3.2x1.8 20 lead ultra thin quad flat no-lead plastic package (utqfn) rev 0, 5/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view typical recommended land pattern top view (1 x 0.70) ( 19x 0 . 60 ) 20 0.10 ( 2. 30 ) (4x) ( 16 x 0 . 40 ) ( 20x 0 . 20 ) c max 0.55 3.20 12 pin 1 id# 6 1.80 b a 19 16x 0.40 5 0 . 05 max. 0 . 00 min. 0 . 2 ref base plane see detail "x" c c 0.10 seating plane 0.05 c m 20x 0.20 m 4 19x 0.40 0.10 11 10 0.10 0.05 ab c c 9 6 pin #1 id 2 1 0.500.10 bottom view view ?a-a? ( 1.0 )
ISL95874, isl95875, isl95876 29 fn7933.0 october 21, 2011 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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